1. Field of the Invention
The invention relates to an apparatus for testing a semiconductor integrated circuit, the apparatus having an ancillary test device placed in the vicinity of a test circuit board which exchanges signals with a semiconductor integrated circuit under test.
2. Background Art
A large-scale analog semiconductor integrated circuit (hereinafter called an “LSI”) is usually tested through use of an analog-only tester. The analog-only tester is configured so as to supply a test input signal to a semiconductor integrated circuit under test (hereinafter called a “DUT”) by way of a test circuit board which exchanges signals with the DUT and receives a test output signal from the DUT and analyzes the output signal. However, in relation to a recent semiconductor integrated circuit, the number of consolidated-type LSIs; that is, a combination of an analog LSI having digital circuitry, more specifically, a combination of an analog LSI, and a logic circuit and a memory circuit, is increasing. If the scale of digital circuitry to be incorporated into the consolidated-type LSI is small and the digital circuitry operates at low speed, the analog-only tester can test the digital circuit by means of low-performance function testing capability incorporated in the analog-only tester. However, in association with a recent fast progression of an on-chip system, the scale of digital circuitry to be incorporated into an analog LSI becomes larger. Hence, testing of the analog LSI through use of the conventional testing capability becomes difficult.
A conceivable countermeasure for improving the circumstances under which testing of an analog LSI becomes difficult is expansion of digital function testing capability incorporated in the analog-only tester. Expansion of the digital function testing capability requires development of an individual custom-designed tester for expansion purpose. Another conceivable countermeasure is to prepare custom-designed testers for an analog circuit, a digital logic circuit, and digital memory, respectively. Plant and equipment investments for a logic-circuit-specific tester and a memory-specific tester are required. Further, an increase in the time required for testing is also feared. Moreover, preparation of a mixed-signal-type tester for a consolidated-type LSI is also conceivable, which requires big-budget investments for a special tester.
Even in the case of a test for a digital LSI, an increase in the scale of a logic circuit and that of a memory circuit, which are to be incorporated into an LSI, is also being pursued. Analogous problems arise in a custom-designed tester compatible with a logic circuit and a memory circuit. Further, similar problems arise in a test for a consolidated LSI formed by providing a digital LSI with an analog circuit.
JP-A-8-179013 and JP-A-2001-83216 describe testers which have a built-in pattern generator and digital function testing capability. However, these patents relate to testers having digital function testing capability; in other words, imparting digital function testing capability to a custom-designed tester. Expansion of the digital function requires development of individual custom-designed testers, as mentioned previously. A tester that cannot address such expansion of digital function capability requires significant modifications, which in turn leads to occurrence of problems pertaining to costs and ease of expansion.
Prior to filing the present patent application, the inventors had already filed JP-A-2002-236143, which proposes an ancillary test device-which is disposed in the vicinity of a test circuit board and has a test circuit for an analog-to-digital conversion circuit and a digital-to-analog conversion circuit—as an apparatus for testing a semiconductor integrated circuit including an analog-to-digital conversion circuit and a digital-to-analog conversion circuit. The ancillary test device tests an analog-to-digital conversion circuit and a digital-to-analog conversion circuit, both being included in an analog circuit, for a consolidated-type LSI embodied by mixedly incorporating an analog circuit into a digital LSI. As a result of an analog-to-digital conversion circuit for testing purpose and a digital-to-analog conversion circuit for testing purpose being provided in the ancillary test apparatus to be disposed in the vicinity of a test circuit board, significant modifications of the tester are not required, and an analog measurement line provided between the tester and a circuit board under test is obviated. Further, an effective test can be performed by the ancillary test device disposed in the vicinity of the circuit board under test while influence of noise on the analog measurement line is eliminated. However, such a tester disclosed in the preceding patent application is also insufficient for further expansion of testing capability.